Nonvolatile semiconductor memory device

ABSTRACT

A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation and claims the benefit of priorityunder 35 U.S.C. § 120 from U.S. Ser. No. 16/274,545, filed Feb. 13,2019, which is a continuation and claims the benefit of priority under35 U.S.C. § 120 from U.S. Ser. No. 15/802,952, filed Nov. 3, 2017, whichis continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 15/389,609 filed Dec. 23, 2016, now U.S. Pat. No.9,812,195, which is a continuation of and claims the benefit of priorityunder 35 U.S.C. § 120 from U.S. Ser. No. 15/080,930, filed Mar. 25,2016, now U.S. Pat. No. 9,543,011, which is a continuation Ser. No.14/589,554, filed Jan. 5, 2015 now U.S. Pat. No. 9,299,426, which is acontinuation of U.S. Ser. No. 13/058,952, filed May 6, 2011 now U.S.Pat. No. 8,964,447, which is a National Stage application ofPCT/JP2009/062019, filed Jun. 24, 2009 and claims the benefit ofpriority under 35 U.S.C. § 119 from JP 2008-208426, filed Aug. 13, 2008,the entire contents of each of which are incorporated herein byreference.

TECHNICAL FIELD

The present invention relates to a nonvolatile semiconductor memorydevice using a variable resistive element of which resistance is storedas data.

BACKGROUND ART

Electrically erasable programmable nonvolatile memories include a flashmemory as well known in the art, which comprises a cell array ofNAND-connected or NOR-connected memory cells having a floating gatestructure. A ferroelectric memory is also known as a nonvolatile fastrandom access memory.

On the other hand, technologies of pattering memory cells much finerinclude a resistance variable memory, which uses a variable resistiveelement in a memory cell as proposed. Known examples of the variableresistive element include a phase change memory device that varies theresistance in accordance with the variation in crystal/amorphous statesof a chalcogenide compound; an MRAM device that uses a variation inresistance due to the tunnel magneto-resistance effect; a polymerferroelectric RAM (PFRAM) memory device including resistive elementsformed of a conductive polymer; and a ReRAM device that causes avariation in resistance on electrical pulse application (Patent Document1).

The resistance variable memory may configure a memory cell with a serialcircuit of a Schottky diode and a resistance variable element in placeof the transistor. Accordingly, it can be stacked easier andthree-dimensionally structured to achieve much higher integration as anadvantage (Patent Document 2).

When data write/erase to the memory cell changes the state of thevariable resistive element, the variable resistive element and thenon-ohmic element produce heat. Therefore, simultaneous data write/eraseto a number of memory cells exerts a larger influence by the heatproduction and in turn results in the loss of data stability. Thisproblem is further actualized by higher integration of the nonvolatilememory.

Patent Document 1

JP 2006-344349A, paragraph 0021

Patent Document 2

JP 2005-522045A

DISCLOSURE OF INVENTION Technical Problem

The present invention therefore has an object to provide a nonvolatilememory capable of realizing fast operation by concurrent write/erase toplural memory cells and relieving the influence by heat produced frommemory cells at the time of operation.

Technical Solution

In an aspect the present invention provides a nonvolatile semiconductormemory device, comprising: a cell array including a plurality of firstlines, a plurality of second lines intersecting the plurality of firstlines, and a plurality of memory cells arranged in matrix and connectedat intersections of the first and second lines between both lines, eachmemory cell containing a serial circuit of an electrically erasableprogrammable variable resistive element of which resistance isnonvolatilely stored as data and a non-ohmic element; and an accesscircuit operative to simultaneously access plural memory cellsphysically separated from each other in the cell array.

In another aspect the present invention provides a nonvolatilesemiconductor memory device, comprising: a cell array including pluralMATs (unit cell arrays) arranged in matrix, each MAT containing aplurality of first lines, a plurality of second lines intersecting theplurality of first lines, and a plurality of memory cells connected atintersections of the first and second lines between both lines, eachmemory cell containing a serial circuit of an electrically erasableprogrammable variable resistive element of which resistance isnonvolatilely stored as data and a non-ohmic element; and a plurality ofaccess circuits connected to the MATs and operative to simultaneouslyaccess memory cells inside the MATs, wherein the plurality of accesscircuits simultaneously access a certain number of memory cells insidecorresponding MATs.

In yet another aspect the present invention provides a nonvolatilesemiconductor memory device, comprising: a cell array including Nm MATs(unit cell arrays) (Nm=an integer of 1 or more) arranged in matrix, eachMAT containing Na first lines (Na=an integer of 1 or more), Nb secondlines (Nb=an integer of 1 or more) intersecting the Na first lines, anda plurality of memory cells connected at intersections of the first andsecond lines between both lines, each memory cell containing a serialcircuit of an electrically erasable programmable variable resistiveelement of which resistance is nonvolatilely stored as data and anon-ohmic element: and a plurality of access circuits connected to theMATs and operative to simultaneously access memory cells inside each ofthe MATs, wherein a memory cell connected to an a-th first line (a=aninteger of 1 to Na) and a b-th second line (b=an integer of 1 to Nb) inan m-th one of the MATs (m=an integer of 1 to Nm) has a logical addressi={(a−1)Nb+(b−1)}Nm+(m−1), the plurality of access circuitssimultaneously access a j-th page (j=an integer of 1 to Na×Nb) composedof Nm memory cells at logical addresses Nm(j−1) through Nm(j−1)+(Nm−1).

Effect of the Invention

In accordance with the present invention, it is made possible to providea nonvolatile memory capable of realizing fast operation by concurrentwrite/erase to plural memory cells and relieving the influence by heatproduced from memory cells at the time of operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a nonvolatile memory according to a firstembodiment of the present invention.

FIG. 2 is a perspective view showing part of a MAT in the nonvolatilememory according to the same embodiment.

FIG. 3 is a cross-sectional view of one memory cell taken along I-I′line and seen from the direction of the arrow in FIG. 2.

FIG. 4 is a schematic cross-sectional view showing an example of avariable resistive element in the same embodiment.

FIG. 5 is a circuit diagram showing a MAT at the time of writing.

FIG. 6 is a circuit diagram showing a MAT at the time of writing on apage basis.

FIG. 7 is a brief diagram showing an example of writing sequence on apage basis.

FIG. 8 is a brief diagram showing another example of writing sequence ona page basis.

FIG. 9 provides a brief diagram (a) showing erasing on a MAT basis and acircuit diagram (b) showing a MAT.

FIG. 10 is a brief diagram showing writing on a page basis in thenonvolatile memory according to the first embodiment.

FIG. 11 is a block diagram showing a cell array in the same embodiment.

FIG. 12 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in the cell array in the same embodiment.

FIG. 13 is a circuit diagram showing part of a row control circuit inthe same embodiment.

FIG. 14 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a second embodiment.

FIG. 15 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a third embodiment.

FIG. 16 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a fourth embodiment.

FIG. 17 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a fifth embodiment.

FIG. 18 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a sixth embodiment.

FIG. 19 is a circuit diagram of a sense amplifier circuit S/A in thesame embodiment.

FIG. 20 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to another embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

The embodiments associated with the nonvolatile memory according to thepresent invention will now be described in detail with reference to thedrawings.

First Embodiment

FIG. 1 is a block diagram of a nonvolatile memory according to a firstembodiment of the present invention.

The nonvolatile memory comprises a plurality of MATs (unit cell arrays)1 arranged in matrix, each including memory cells using resistancevariable elements, as in a later-described ReRAM (Resistive RAM). EachMAT 1 includes an access circuit, that is, a column control circuit 2and a row control circuit 3. The column control circuit 2 includes asense amplifier circuit (not shown) operative to sense/amplify dataappeared on a bit line from a memory cell. It controls bit lines BL inthe MAT 1 and executes erasing data from the memory cells, writing datato the memory cells, and reading data out of the memory cells. The rowcontrol circuit 3 is operative to select from among word lines WL in theMAT 1 and apply voltages required for erasing data from the memorycells, writing data to the memory cells, and reading data out of thememory cells.

A data I/O buffer 4 is connected to an external host, not shown, via anI/O line to receive write data, receive an erase instruction, provideread data, and receive address data and command data.

The data I/O buffer 4 is connected to a read/write circuit (hereinafterreferred to as “R/W circuit”) 8. The data I/O buffer 4 sends receivedwrite data via the R/W circuit 8 to the column control circuit 2 andreceives read-out data from the column control circuit 2 via the R/Wcircuit 8 and provides it to external. An address fed from external tothe data V/O buffer 4 is sent via an address register 5 to the columncontrol circuit 2 and the row control circuit 3. A command fed from thehost to the data I/O buffer 4 is sent to a command interface 6. Thecommand interface 6 receives an external control signal from the hostand decides whether the data fed to the data I/O buffer 4 is write data,a command or an address. If it is a command, then the command interfacetransfers it as a received command signal to a controller 7. Thecontroller 7 manages the entire nonvolatile memory and receives commandsfrom the host to execute read, write, erase, and data I/O management.The external host can also receive status information managed by thecontroller 7 and decide the operation result. The status information isalso utilized in control of write and erase.

The controller 7 controls the R/W circuit 8. Under this control, the R/Wcircuit 8 is allowed to provide a pulse of any voltage/current at anytiming. The pulse formed herein can be transferred to any line selectedby the column control circuit 2 and the row control circuit 3.

As shown in the figure, the column control circuit 2, the row controlcircuit 3 and the R/W circuit 8 are formed coplanar with the MAT 1though these peripheral circuit elements other than the MATs 1 can beformed in the Si substrate immediately beneath the MATs 1 formed in awiring layer. Thus, the chip area of the nonvolatile memory can be madealmost equal to a total area of plural MATs 1.

FIG. 2 is a perspective view of part of the MAT 1, and FIG. 3 is across-sectional view of one memory cell taken along I-I′ line and seenin the direction of the arrow in FIG. 2.

There are plural first lines or word lines WL0-WL2 disposed in parallel,which cross plural second lines or bit lines BL0-BL2 disposed inparallel. A memory cell MC is arranged at each intersection of bothlines as sandwiched therebetween. Desirably, the first and second linesare composed of heat-resistive low-resistance material such as W, WSi,NiSi, CoSi.

The memory cell MC comprises a serial connection circuit of a variableresistive element VR and a non-ohmic element NO as shown in FIG. 3.

The variable resistive element VR can vary the resistance with current,heat, or chemical energy on voltage application. Arranged on an upperand a lower surface thereof are electrodes EL1, EL2 serving as a barriermetal layer and an adhesive layer. Material of the electrodes mayinclude Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO,Al, PtIrO_(x), PtRhO_(x), Rh, TaAlN. A metal film capable of achievinguniform orientation may also be interposed. A buffer layer, a barriermetal layer and an adhesive layer may further be interposed.

Available examples of the variable resistive element VR include: onethat changes the resistance in accordance with a phase change betweenthe crystalline state and the amorphous state, such as a chalcogenide(PCRAM); one that changes the resistance by precipitating metal cationsto form a bridge (conducting bridge) between electrodes and ionizing theprecipitated metal to destruct the bridge (CBRAM): and one that changesthe resistance by applying a voltage or current (ReRAM) although thereis no agreed theory (the factors in the resistance variation are roughlydivided into two: one that causes a variation in resistance inaccordance with the presence/absence of charge trapped in charge trapspresent in the electrode interface: and one that causes a variation inresistance in accordance with the presence/absence of the conductionpath due to an oxygen loss and so forth).

FIG. 4 shows an example of the ReRAM. The variable resistive element VRshown in FIG. 4 includes a recording layer 12 arranged between electrodelayers 11, 13. The recording layer 12 is composed of a compositecompound containing at least two types of cation elements. At least oneof the cation elements is a transition element, of which d-orbit isincompletely filled with electrons, and the shortest distance betweenadjacent cation elements is 0.32 nm or lower. Specifically, it isrepresented by a chemical formula A_(x)M_(y)X_(z) (A and M are differentelements) and may be formed of material having a crystal structure suchas a spinel structure (AM₂O₄) an ilmenite structure (AMO₃), a delafossite structure (AMO₂), a LiMoN₂ structure (AMN₂), a wolframite structure(AMO₄), an olivine structure (A₂MO₄), a hollandite structure (AMO₂), aramsdellite structure (AMO₂), and a perovskite structure (AMO₃).

In the example of FIG. 4, A comprises Zn, M comprises Mn, and Xcomprises O. In the recording layer 12, a small white circle representsa diffused ion (Zn), a large white circle represents an anion (O), and asmall black circle represents a transition element ion (Mn). The initialstate of the recording layer 12 is the high-resistance state. When theelectrode layer 11 is kept at a fixed potential and the electrode layer13 is supplied with a negative voltage, part of diffused ions in therecording layer 12 migrate toward the electrode layer 13 to reducediffused ions in the recording layer 12 relative to anions. The diffusedions arrived at the electrode layer 13 accept electrons from theelectrode layer 13 and precipitate as a metal, thereby forming a metallayer 14. Inside the recording layer 12, anions become excessive andconsequently increase the valence of the transition element ion in therecording layer 12. As a result, the carrier injection brings therecording layer 12 into electron conduction and thus completes setting.On regeneration, a current may be allowed to flow, of which value isvery small so that the material configuring the recording layer 12causes no resistance variation. The programmed state (low-resistancestate) may be reset to the initial state (high-resistance state) bysupplying a large current flow in the recording layer 12 for asufficient time for Joule heating, thereby facilitating the oxidationreduction reaction in the recording layer 12. Application of an electricfield in the opposite direction from that at the time of setting mayalso allow resetting.

The non-ohmic element NO may include various diodes such as a Schottkydiode, a PN-junction diode, a PIN diode, and may have a MIM(Metal-Insulator-Metal) structure, and a SIS (Silicon-Insulator-Silicon)structure. In this case, electrodes EL2, EL3 forming a barrier metallayer and an adhesive layer may be interposed. If a diode is used, fromthe property thereof, it can perform the unipolar operation. In the caseof the MIM structure or SIS structure, it can perform the bipolaroperation. The non-ohmic element NO and the variable resistive elementVR may be placed in the opposite relation to that in FIG. 3. Thenon-ohmic element NO may be reversed in polarity.

Operation of the present embodiment is described next.

FIG. 5 is a circuit diagram showing the MAT 1 at the time of writing(setting) in the nonvolatile memory.

The MAT 1 includes, for example, 1024 first lines or word lines WL and,for example, 512 second lines or bit lines BL crossing these word linesWL. There are 1024×512 intersections of the lines, at which connectedare memory cells MC each including the non-ohmic element NO or a diodeD1 having an anode connected to the word line WL, and the variableresistive element VR connected between the cathode of the diode D1 andthe bit line BL. The size of the MAT 1 can be determined inconsideration of voltage drops on the word line WL and the bit line BL,CR delays, processing speeds of data writing, and so forth. It may havean arbitrarily selected size such as 1024×2048 other than the MAT 1shown in FIG. 5.

Subsequently, writing to the MAT 1 is described. The followingdescription is given to writing to the memory cell MC1 connected at theintersection of the word line WL1 and the bit line BL1, surrounded bythe dotted line in FIG. 5.

In this case, the word line WL1 connected to the memory cell MC1 issupplied with a word line set voltage Vsetwl (3 V, for example), and thebit line BL1 is supplied with a bit line set voltage Vsetbl (0 V, forexample). As a result, in the memory cell MC1, the diode D1 is forwardbiased and accordingly the variable resistive element VR makes atransition to the low-resistance state to complete writing.

On the other hand, the word lines WL2, . . . connected to other memorycells MC are supplied with a word line non-selection voltage Vnswl (0 V,for example) and the bit lines BL2, . . . are supplied with a bit linenon-selection voltage Vnsbl (3 V, for example). As a result, in thememory cells MC, the diode D1 is reverse biased and the variableresistive element VR makes no transition in the resistance state becauseno current flows therein.

Writing is described above while erasing (resetting) is similar towriting except that a lower reset voltage than the set voltage isapplied for a longer period of time than that for the set voltage toproduce Joule heat from the memory cells MC.

Thus, in writing only to one memory cell MC1, other memory cells MCproduce no heat and accordingly heat produced from the entire cell arrayinfluences less and causes no problem. In this case, though, the memorycells MC are subjected one by one to writing. Accordingly, complete ofwriting to all the memory cells contained in the cell array takes aconsiderable length of time.

A method of solving the above problem comprises writing to a pluralityof memory cells MC simultaneously as considered. Hereinafter, theplurality of memory cells MC simultaneously accessed is referred to as apage.

FIG. 6 is a circuit diagram showing the MAT 1 at the time of writing ona page basis. The following description is given to the case forsimultaneously writing to the memory cells MC2-MC4 connected to the wordline WL1, surrounded by dotted line in FIG. 6.

In this case, the word line WL1 is supplied with a word line set voltageVsetwl (3 V). On the other hand, the bit lines BL1-BL3 connected to thememory cells MC2-MC4 are supplied with a bit line set voltage Vsetbl,that is, 0 V. As a result, in the memory cells MC2-MC4 connected at theintersections of the word line WL1 and the bit lines BL1-BL3, the diodeD1 is forward biased and accordingly the variable resistive element VRin the memory cells MC2-MC4 makes a transition to the low-resistancestate to execute writing on a page basis. On the other hand, in thememory cells MC connected to non-selected word lines WL2, WL3, the diodeD1 is not forward biased, and the variable resistive element VR in thememory cells MC allows no current to flow therein, and makes notransition in the resistance state.

Writing is described above while erasing is similar to writing exceptthat a lower reset voltage than the set voltage is applied for a longerperiod of time than that for the set voltage to produce Joule heat fromthe memory cells MC.

Thus, in writing to plural memory cells MC connected to the word lineWL1, simultaneous writing can be executed. Accordingly, it is possibleto execute write processing faster than one-by-one writing.

In this case, however, plural adjacent memory cells MC produce heatsimultaneously. Therefore, the influence from adjacent memory cells andthe influence by heat produced from the entire cell array are large andmay result in the loss of the stability of the nonvolatile memory.

Subsequently, writing to the entire cell array on a page basis isdescribed.

FIGS. 7 and 8 are brief diagrams showing examples of writing sequence ona page basis.

FIG. 7 shows the case where sequential writing is executed to pages inthe same MAT 1 and, after completion of writing to pages contained inthe MAT 1 (S1-S3), sequential writing is executed to pages in the nextMAT 1 (S4-S6).

In this case, because of writing on a page basis, heat simultaneouslyproduced from plural memory cells MC largely influences. In addition,because of continuous writing to adjacent pages in a shorter time, thequantity of residual heat largely influences and may extremelydeteriorate the stability around the page during writing.

FIG. 8 shows sequential writing to each MAT 1 page by page (S11-S18) andthen writing to a different not-written page in each MAT 1 again (S19-).Through the repetition of writing on a page basis, writing can beexecuted to the entire cell array.

In this case, after writing to one page belonging to a certain MAT,writing is executed to one page belonging to a different MAT physicallyseparated therefrom. Accordingly, compared with the case of FIG. 7, thepage during writing is hardly susceptible to heat produced by writing toother pages and therefore the stability can be improved. Even in thiscase, however, with regard to writing to individual pages, pluralphysically proximate memory cells MC connected to one word line WLproduce heat at the same time unchangeably. Therefore, it is notsufficient to improve the stability of the nonvolatile memory.

As for erasing, it is possible to execute batch erasing on a MAT 1 basisas can be considered. The following description is given to erasingexecuted to a MAT 1 surrounded by the dotted line in FIG. 9(a). FIG.9(b) is a circuit diagram showing the MAT 1 surrounded by the dottedline in FIG. 9(a).

In this case, as in FIG. 9 (b), all word lines WL are supplied with aword line reset voltage Vresetwl (1 V, for example) lower than a wordline set voltage Vsetwl (3 V, for example). In addition, all bit linesBL are supplied with a bit line reset voltage Vresetbl (0 V, forexample). As a result, in all memory cells MC, the diode D1 is forwardbiased and the resistance state of the variable resistive element VRmakes a transition to the high-resistance state to complete erasing.

Thus, erasing on a MAT 1 basis makes it possible to execute eraseprocessing faster than erasing executed to the memory cells MC one byone or page by page. In this case, however, a number of memory cells MCadjacent to each other along the word line WL or along the bit line BLproduce heat simultaneously. Therefore, the instability of thenonvolatile memory is increased obviously more than erasing executed tothe memory cells MC one by one or page by page.

Then, in the present embodiment, memory cells MC are selected one by onefrom plural MATs 1 as shown in FIG. 10, and the selected memory cells MCare subjected to batch erasing.

Thus, even in writing/erasing to a page surrounded by the dotted line inFIG. 10, because the memory cells MC are separated from each other, theheat produced from each memory cell MC can be relieved to influence onother memory cells MC. In addition, because of operation on a pagebasis, the processing time is not inferior to the operation on a pagebasis shown in FIGS. 6 and 7.

A specific configuration of the present embodiment is described below.

FIG. 11 is a block diagram of the cell array in the first embodiment.

The cell array in FIG. 11 is divided into 4 rows along the extension ofthe word line WL or in the x direction and 3 columns along the extensionof the bit line EL or in the y direction, thus 12 blocks BLK in total.The following description is given on the assumption that the blockslocated on the upper stage in FIG. 11 are denoted with BLK #0. #1, #2,#3 from the left, the blocks located on the middle stage with BLK #4,#5, #6, #7 from the left, and the blocks located on the lower stage withBLK #8, #9, #10, #11.

Each block BLK includes a respective MAT. Each MAT is assumed to have 8memory cells in the x direction and 8 memory cells in the y direction,thus 64 in total for simplicity of description. Memory cells in the MATare assigned with physical addresses, which increase one by one in the xdirection and 8 by 8 in the y direction. In a word, memory cells at theupper left corner, the upper right corner, the lower left corner, andthe lower right corner in each MAT are assigned with physical addresses0, 7, 56, 73.

Each MAT is provided with a column control circuit 2 and a row controlcircuit 3.

The column control circuits 2 in the MATs located in the blocks BLK #0;#4, #8 aligned in the y direction are connected via transfer transistorsT0, T4, T8 to an IO pad 0. Similarly, the column control circuits 2 inthe MATs located in the blocks ELK #1, #5, #9 are connected via transfertransistors T1, T5, T9 to an IO pad 1, the column control circuits 2 inthe MATs located in the blocks BLK #2, #6, #10 are connected viatransfer transistors T2, T6, T10 to an IO pad 2, and the column controlcircuits 2 in the MATs located in the blocks BLK #3, #7, #11 areconnected via transfer transistors T3, 17, T11 to an IO pad 3,respectively. The transfer transistors T0-T3 aligned in the x directionhave respective gates, which are supplied with a common input dataselection signal IDST0. Similarly, the transfer transistors T4-T7 andT8-T11 have respective gates, which are supplied with common input dataselection signals IDST1 and IDST2, respectively. The input dataselection signals IDST0-2 are signals determined on the basis of inputaddresses.

The following description is given to assignment of logical addresses tothe cell array configured above.

FIG. 12 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in the cell array in the present embodiment.

The MAT #0-#11 are arranged in the blocks BLK #0-#11 shown in FIG. 11,respectively.

If each memory cell has a physical address i (i=0, 1, . . . ), a logicaladdress of each memory cell in MATm is assigned with M+12×i as shown inFIG. 12.

The following description is given to writing on a page basis to thecell array assigned with logical addresses in this way. In this case,one page contains 12 memory cells, and a j-th page (j=1, 2, . . . ) iscomposed of memory cells at logical addresses (j−1)×12 through(j−1)×12+11. For example, the 2nd page is composed of memory cells atlogical addresses #12-#23.

In general, in the case where the number of MATs is Nm (Nm=an integer of1 or more), the number of word lines WL in each MAT is Na (Na=an integerof 1 or more), and the number of bit lines EL is Nb (Nb=an integer of 1or more), a memory cell connected to an a-th word line WL (a=an integerof 1 to Na) and a b-th bit line BL (b=an integer of 1 to Nb) has alogical address i, which can be represented by {(a−1)Nb+(b−1)}Nm+(m−1).In this case, a j-th page (j is an integer of 1 to Na×Nb) includes Nmmemory cells at logical addresses Nm(j−1) through Nm(j−1)+(Nm−1).

Initially, input data fed from external is transferred to the columncontrol circuit 2 contained in each MAT 1 via the IO pad. Theconfiguration of FIG. 12 includes 4 IO pads. Accordingly, when inputdata is transferred to the column control circuits 2 contained in allthe 12 MATs, the input data is divided into 3 pieces, which are thentransferred at different x. Specifically, first 4 bits of the input dataare prepared on the IO pads 0-3. Thereafter, the input data selectionsignal IDST0 is activated (“H”) to turn on the transfer transistorsT0-T3 to connect the IO pads 0-3 with the column control circuits 2 inthe MAT #0-#3. Thus, the input data bits on the IO pads 0-3 aretransferred to the column control circuits 2 in the MAT #0-#3.Subsequently, next 4 bits of the input data are prepared on the IO pads0-3. Thereafter, the input data selection signal IDST1 is activated(“H”) to turn on the transfer transistors T4-T7 to connect the IO pads0-3 with the column control circuits 2 in the MAT #4-#7. Thus, the inputdata bits on the IO pads 0-3 are transferred to the column controlcircuits 2 in the MAT #4-#7. Similarly, subsequent 4 bits of the inputdata are transferred to the column control circuits 2 in the MAT #8-#11.Thus, one bit of the input data can be prepared in the column controlcircuits 2 in all the MAT #0-#11. The input data selection signalsIDST0-2 are herein controlled such that they are activated sequentiallyat operation cycles.

In this state, simultaneously in the MATs, the word line WL connected tothe memory cell at a physical address #0 is supplied with a word lineset voltage Vsetwl (3 V), and the bit line BL is supplied with a bitline set voltage Vsetbl (3 V or 0 V). On the other hand, the word linesWL connected to other memory cells are supplied with a word linenon-selection voltage Vnswl (0 V), and the bit lines BL are suppliedwith a bit line non-selection voltage Vsetbl (3 V). As a result, theinput data at the column control circuits in the MATs is held in thememory cell at the physical address #0 to complete the 1st page writing.

With repetitions of the above over all the pages, writing to the entirecell array can be completed.

In accordance with the configuration of FIG. 11, 12 bits of one pageinput data are divided and transferred to the column control circuits inthe MATs. A preparation of more IO pads than those in the above exampledecreases the number of transfers. For example, if there are 12 IO pads,one page data can be prepared with one transfer. On the other hand, ifthere are fewer IO pads, an increased number of transfers can respond tosuch the case.

The following description is given to operation of the row controlcircuit 3 for realizing such write.

FIG. 13 is a circuit diagram showing part of the row control circuit 3.

The row control circuit 3 in each MAT 1 is supplied with an address forselecting the MAT via a global word line (Global Select) and localaddress lines (Block Select 1-3) arranged for reducing the number ofaddress lines, and with an address for selecting a word line in the MATvia local address lines, not shown. As shown in FIG. 13(a), the globalword line (Global Select) and the local address lines (Block Select 1-3)are used to activate transistors P1 and N1-N3 to select the MAT. The rowcontrol circuit 3 comprises invertors IV4, IV5 that are set or reset inaccordance with whether each MAT is a failed block or not, and a latchcircuit including transistors N6, N8, thereby isolating the failed blocktherefrom. When the transistors P1 and N1-N4 turn on, a transistor P2turns on. As a result, a transfer gate select n signal rises viainverters IV1, IV2 and a transfer gate select signal falls in sync witha trigger signal via an inverter IV3 and a transistor N5.

On receipt of these transfer gate select signal and select n signal, asshown in FIG. 13(b), a set voltage, Vsetwl+α, is supplied to a transfergate, not shown, via transistors N9 and P3. In addition, word lineselection signals obtained by decoding the local address are used toon/off control the transfer gate, not shown, via transistors N11-N14 ofwhich gates are specially controlled via the transistor N10. Thus, theset voltage, Vsetwl+α, is transferred to the selected word line WL inthe selected MAT.

Among these circuits, internal logics may be configured to select pluralMATs at the same time with the global word line and the local addresslines.

Thus, the present embodiment makes it possible to execute simultaneouswriting to plural memory cells contained in plural pages and accordinglyreduce the time required for writing shorter than writing to the memorycells one by one. Further, simultaneous write target memory cells aredispersed in different MATs and physically separated from each other.Accordingly, it is possible to provide a high-stability nonvolatilememory capable of exerting less influence by heat produced from memorycells, similar to writing to the memory cells one by one.

Second Embodiment

FIG. 14 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a second embodiment.

The assignment sequence of logical addresses belonging to the MATs ischanged from that in the first embodiment.

The logical addresses to be assigned to the memory cells belonging tothe MATs are assigned with a difference of 12, like in the case of thefirst embodiment. In the case of the present embodiment, however, eachMAT is logically divided into two in the x direction, and thus in MATn,a memory cell at a physical address #0 is assigned with a logicaladdress n; a memory cell at a physical address #4 is assigned with alogical address n+12: a memory cell at a physical address #2 is assignedwith a logical address n+24; and a memory cell at a physical address #5is assigned with a logical address n+36. Thus, in the presentembodiment, logical addresses are assigned alternately to a left portion1 a and a right portion 1 b in a MAT.

In this case, the memory cells at logical addresses #0-#11 contained inthe 1st page and the memory cells at logical addresses #12-#23 containedin the 2nd page in the same MAT are arranged at a certain distance fromeach other in the x direction.

In a word, the present embodiment makes it possible to relieve heatproduced from each of the memory cells contained in one page toinfluence on others. In addition, as for the positional relations, thememory cells contained in different pages are arranged at a certaindistance from each other. Accordingly, heat produced from the memorycells contained in the page subjected to writing immediately beforehardly influences on operation of the page during writing. With thisregard, it is possible to improve the stability more than the case ofthe first embodiment.

Third Embodiment

FIG. 15 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a third embodiment.

The logical addresses to be assigned to the memory cells belonging tothe MATs are assigned with a difference of 12, like in the cases of thefirst and second embodiments. In the case of the present embodiment,each MAT is logically divided into two in the y direction, and thus inMATn, a memory cell at a physical address #0 is assigned with a logicaladdress n; a memory cell at a physical address #32 is assigned with alogical address n+12; a memory cell at a physical address #1 is assignedwith a logical address n+24; and a memory cell at a physical address #33is assigned with a logical address n+36. Thus, in the presentembodiment, logical addresses are assigned alternately to an upperportion 1 c and a lower portion 1 d in a MAT.

Also in the present embodiment, memory cells contained in a j-th pageand a (j+1)-th page are arranged at a certain distance from each otherin the y direction. Accordingly, it is possible to exert the same effectas that in the second embodiment.

Fourth Embodiment

FIG. 16 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a fourth embodiment.

The logical addresses to be assigned to the memory cells belonging tothe MATs are assigned with a difference of 12, like in the cases of thefirst through third embodiments. In the case of the present embodiment,each MAT is logically divided into two, both in the x direction and inthe y direction, four in total, and thus in MATn, a memory cell at aphysical address #0 located at the upper left portion 1 e is assignedwith a logical address n: a memory cell at a physical address #4 locatedat the upper right portion 1 f is assigned with a logical address n+12:a memory cell at a physical address #32 located at the lower leftportion 1 g is assigned with a logical address n+24; and a memory cellat a physical address #36 located at the lower right portion 1 h isassigned with a logical address n+36. Thus, in the present embodiment,logical addresses are assigned sequentially to the upper left portion 1e, the upper right portion 1 f, the lower left portion 1 g, and thelower right portion 1 h in a MAT.

In the present embodiment, memory cells contained in j-th, (j+1)-th,(j+2)-th and (j+3)-th pages are arranged at a certain distance from eachother in the x direction and in they direction. Accordingly, it ispossible to relieve the influence by writing to one page so as not toexert on others more than the first through third embodiments.

Fifth Embodiment

A fifth embodiment is directed to writing to a page containing 12 memorycells in two operations on a half-page basis.

FIG. 17 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to the fifth embodiment.

The assignment of logical addresses to memory cells in the MATs issimilar to the case of the second embodiment. In the present embodiment,though, MATn and MAT (n+1) are arranged with one MAT interposedtherebetween. Specifically. MAT #0-#5 are arranged in the blocks BLK #0,#2, #4. #6, #8, #10, and MAT #6-#11 in the blocks BLK #1, #3, #5, #7,#9, #11.

With this assignment of logical addresses, first, memory cells atlogical addresses #0-#5 of memory cells contained in the 1st page aresubjected to writing. Next, the remaining memory cells at logicaladdresses #6-#11 contained in the 1st page are subjected to writing.This writing in two operations executes writing to one page. Repetitionsof the above can complete writing to the entire cell array.

In accordance with the present embodiment, writing to one page isdivided into two. Accordingly, the write processing is made slower thanthose in the first through fourth embodiments though memory cellsoperable on first writing on a page basis are arranged with one MATinterposed therebetween in the x direction. Therefore, it is possible torelieve the influence by heat produced from memory cells lower thanthose in the first through fourth embodiments. Further, power consumedat a time can be reduced effectively for power consumption measures.

In the present embodiment, writing to one page is divided into twothough this number may be set arbitrarily in consideration of the writeprocessing speed, the power consumption and so forth.

Sixth Embodiment

FIG. 18 is a block diagram showing an arrangement of MATs and logicaladdresses of memory cells in a cell array in a nonvolatile memoryaccording to a sixth embodiment.

The present embodiment comprises a new column control circuit 2′ inplace of the column control circuit 2 in the first embodiment.

Different from the column control circuit 2, the column control circuit2′ characteristically includes plural sense amplifier circuits S/A,which allow selection of plural bit lines in each MAT. Accordingly, itis possible to execute simultaneous writing to memory cellscorresponding to the sense amplifier circuits S/A in number among pluralmemory cells connected to the same word line.

Subsequently, a sense amplifier circuit S/A shown in FIG. 19 isdescribed.

A node TDC shown in FIG. 19 is a sense node for sensing the bit linevoltage as well as a data storage node for temporarily storing data. Thenode TDC is connected via a clamp NMOS transistor N101 to the bit lineBL. The clamp transistor N101 is operative to clamp the bit line voltageat the time of read and transfer it to the node TDC. The node TDC isconnected to a precharge NMOS transistor N102 for precharging the bitline BL and the node TDC.

The node TDC is connected via transfer NMOS transistors N103, N104 todata storage nodes PDC, SDC in data latches 112, 113. The data latch 112is a data storage circuit operative to hold read data and write data.The data latch 113 is a data cache arranged between the data latch 112and data lines 10, Ion and used in temporarily storing read data orwrite data.

The data latch 113 has nodes, which are connected to the data line pair10, IOn in a data bus via selection gate transistors N105, N106 drivenby a column selection signal CSL.

The selection gate transistors N105, N106 are automatically turnedon/off in association with the column address.

In order to obtain a certain threshold distribution, data write isexecuted by repeating write voltage application and write verify. Verifyis executed at every sense amplifier contained in each MAT. It isrequired to determine write data in the next cycle in accordance withthe verify result.

An NMOS transistor N111 given a voltage VPRE on the drain has a gate,which serves as a data storage node DDC for temporarily saving andholding write data held on the node PDC in the data latch 112 at thetime of write. Write data on the node PDC in the data latch 112 istransferred to the data storage node DDC via a transfer NMOS transistorN114. The voltage VPRE is turned to Vdd or Vss selectively.

The NMOS transistor N111 and an NMOS transistor N117 interposed betweenthe former and the data storage node TDC make it possible to set data onthe data storage node TDC in accordance with the data on the datastorage node DDC. Namely, the NMOS transistors N111, N117 configure awrite-back circuit operative to write the next-cycle write data back tothe storage node TDC.

In accordance with pieces of data held on the data storage nodes DDC,BDC, and in accordance with the selection of the drain voltage VPRE onthe transistors N111, N112, the data node TDC is forcibly discharged(that is, set to “L” level) or charged (that is, set to “H” level) atthe time of verify read, as can be controlled.

The data latch 112 is connected to a verify check circuit 114. The datalatch 112 has one node connected to the gate of an NMOS transistor N122,that is, a check transistor, which has a source grounded via an NMOStransistor N121 controlled by a check signal CHK1, and a drain connectedvia paralleled NMOS transistors N123, N124 to a common signal line COMshared by sense units in one page. The NMOS transistors N123, N124 haverespective gates, which are controlled by a check signal CHK2 and thenode TDC.

Only if “0” write is determined insufficient as a result of verify read,write-back is executed such that the node PDC in the data latch 112becomes “L” (“0”). Namely, after completion of one page write, the datalatches 112 are verify-controlled to exhibit all “1”.

At the time of data write, the verify check circuits 114 turn on insense units in one page after verify read. If write is not completed ina certain sense unit, the verify check circuit 114 discharges the commonsignal line COM previously charged to “H”. When the data latches 112 inone page reach the state of all “1”, the common signal line COM is notdischarged and holds “H”, which becomes a pass flag indicative of writecompletion.

In the present embodiment, there may be 4 bits of data input in one timeas described in the first embodiment. In this case, not only data loadcan be executed bit by bit to 4 MATs, but also the following data inputcan be executed because each MAT includes plural sense amplifiercircuits S/A.

For example, each MAT includes 16 sense amplifier circuits, 4 bits ofinput data are loaded to one MAT four times successively. Sequentialrepetitions of this operation to the following MATs allow data load tobe executed to all MATs.

In a further example, first 4 bits of input data are loaded in a certainMAT and the next 4 bits of input data are loaded in the next MAT.Repetitions of the above operation make it possible to adjust the numberof pieces of data loaded in the MATs, thereby adjusting the number ofMATs simultaneously operative at the time of write and at the time oferase, or the number of sense amplifier circuits S/A.

The number of sense amplifier circuits S/A contained in one MAT can bedetermined arbitrarily in consideration of the arrangement spaceimmediately beneath the MAT, power consumption at the time of erasing,the influence by heat produced from memory cells, and so forth. Further,the number of MATs simultaneously operative and the number of memorycells (or sense amplifier circuits S/A) simultaneously operative in oneMAT can be controlled as described above and accordingly more flexibledesign can be achieved.

For example, in the case of the present embodiment, the number of senseamplifier circuits S/A contained in one MAT can be determined around16-32 in consideration of the space arrangement immediately beneath thecell array. In this case, at the time of write with relatively smallpower consumption and less influence by heat produced from memory cells,the number of memory cells simultaneously operative in one MAT becomes16-32 similar to the sense amplifier circuits S/A. On the other hand, atthe time of erase with larger power consumption and larger influence byheat produced from memory cells than those at the time of write, thenumber of MATs simultaneously operative and the number of memory cellssimultaneously operative in one MAT are controlled smaller, therebyensuring the fast operation at the time of write while ensuring thestability at the time of erase.

The present embodiment makes it possible to exert the same effect as thefirst embodiment and additionally execute faster write processing thanthe first embodiment.

The column control circuit 2′ of the present embodiment is similarlyapplicable to the second through fifth embodiments.

OTHERS

The embodiments of the present invention have been described abovethough the present invention is not limited to the above embodiments.

For example, if MAT #11, . . . , #0 are arranged in the blocks BLK #0, .. . , #11 in the cell array as shown in FIG. 20, the MATs may bearranged or assigned with logical addresses such that mutual positionsof memory cells contained in each page, or mutual positions of memorycells contained in different pages are separated from each other.

In the above embodiments, writing is mainly described though erasing isalso executed similarly.

The present invention is also applicable to various semiconductor memorydevices other than the nonvolatile memory.

1. A nonvolatile semiconductor memory device, comprising: a cell arrayincluding a plurality first lines, a plurality of second linesintersecting said plurality of first lines, and a plurality of memorycells arranged in matrix and connected at intersections of said firstand second lines between both lines, each memory cell containing aserial circuit of an electrically erasable programmable variableresistive element of which resistance is nonvolatilely stored as dataand a non-ohmic element; and an access circuit operative tosimultaneously access plural memory cells physically separated from eachother in said cell array.